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LT4351 MOSFET Diode-OR Controller
FEATURES
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DESCRIPTIO
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Low Loss Replacement for ORing Diode in Multiple Sourced Power Supplies External N-Channel MOSFETs for High Current Capability Internal Boost Regulator Supply for MOSFET Gate Drive Wide Input Range: 1.2V to 18V Fast Switching MOSFET Gate Control Input Under and Overvoltage Detection STATUS and FAULT Outputs for Monitoring Internal MOSFET Gate Clamp Available in a 10-pin MSOP
The LT4351 creates a near-ideal diode using external single or back-to-back N-channel MOSFETs. This ideal diode function permits low loss ORing of multiple power sources. Power sources can easily be ORed together to increase total system power and reliability with minimal effect on supply voltage or efficiency. Disparate power supplies can be efficiently ORed together. The IC monitors the input supply with respect to the load and turns on the MOSFET(s) when the input supply is higher. If the MOSFET's RDS(ON) is sufficiently small, the LT4351 will regulate the voltage across the MOSFET(s) to 15mV. A STATUS pin indicates the MOSFET on state. An internal boost regulator generates the MOSFET gate drive voltage. Low operating voltage allows for OR'ing of supplies as low as 1.2V. The LT4351 will disable power passage during undervoltage or overvoltage conditions. These voltages are set by resistive dividers on the UV and OV pins. The undervoltage threshold has user programmable hysteresis. Overvoltage detection is filtered to reduce false triggering. The LT4351 is available in a 10-pin MSOP.
APPLICATIO S
s s s s
Paralleled Power Supplies Uninterrupted Supplies High Availability Systems N + 1 Redundant Power Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
Dual 5V Redundant Supply
Si4862DY 5V 10F POWER SUPPLY 1 1F MBR0530 SW 4.7H UV STATUS FAULT OV 1.47k 1% GND STATUS FAULT GND OV 1.47k 1%
4351 TA01
Si4862DY 5V COMMON 10F POWER SUPPLY 2 GATE VIN VDD 1F MBR0530 SW UV 4.7H 5V
CLOAD
RLOAD
VIN VDD
GATE
OUT
OUT
24.9k 1% 232 1%
LT4351
LT4351
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24.9k 1% 232 1%
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LT4351
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW GATE VDD VIN SW GND 1 2 3 4 5 10 9 8 7 6 OUT STATUS FAULT UV OV
VIN Voltage ............................................... - 0.3V to 19V OUT Voltage ............................................ - 0.3V to 19V VDD Voltage ............................................. - 0.3V to 30V FAULT, STATUS Voltages ........................ - 0.3V to 30V FAULT, STATUS Current ........................................ 8mA UV, OV Voltages ........................................ - 0.3V to 9V SW Voltage .............................................. - 0.3V to 32V Operating Temperature Range LT4351C .................................................. 0C to 70C LT4351I .............................................. - 40C to 85C Junction Temperature (Note 2) ............................ 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT4351CMS LT4351IMS MS PART MARKING LTZZ LTA1
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 120C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VIN IVIN VUV(TH) IUV(HYST) IUV VOV(TH) IOV VF(ON) IF(OFF) Boost Supply VBR tOFF ISWLIM Gate Drive VIOR VGL VG(MAX) VGOFF IGSO IGSK Input to Output Regulated Voltage Gate Voltage Limit Maximum Gate Voltage Gate Off Voltage Gate Source Current Gate Sink Current Boost Regulation Trip Voltage Boost Supply Off Time Boost Supply Switch Current Limit PARAMETER Operating Range VIN Supply Current Supply and Protection
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = VOUT = 5V, VDD = 16.1V, VUV = 0.4V, VOV = 0.2V, GATE Open, unless otherwise specified.
CONDITIONS
q
MIN 1.2
TYP
MAX 18
UNITS V mA mA mV A nA mV nA V A V ns mA mV V V V A A
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VIN = 1.2V, VOUT = 1.1V, VDD = 12.3V VIN = 18V, VOUT = 17.9V, VDD = 29.1V Difference Between IUV at VUV(TH) + 10mV and VUV(TH) - 10mV VUV = VUV(TH) + 10mV OV Rising VOV = VOV(TH) - 10mV IF = 5mA In Fault Condition VF = 30V, VIN = 4.9V Measured as VDD to VIN, Rising Edge
q q q q q q q q q
1.41 1.71 290 7 300 10 -100 290 300 -100 0.14 0.04 10.2 350 4 10.7 600 450 15 -2.3 7 7.4 0.16 0.670 0.670
2.0 2.1 310 13 -400 310 -400 0.25 1 11.1 650 25 -3 7.8 0.30
Undervoltage Turn-Off Voltage Threshold UV Falling IUV Hysteresis UV Input Bias Current Overvoltage Threshold OV Input Bias Current FAULT Pin On Voltage FAULT Pin Leakage Current
q q
q
VIN = 5V, VOUT = 4.9V, VDD = 13V Measured with Respect to VDD VIN = 5V, VOUT = 4.9V, VDD = 16.1V Measured with Respect to VOUT VOUT = 5.1V VOUT = 4.9V, VGATE = 9V VOUT = 4.9V, VGATE = 9V
q q q
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LT4351
ELECTRICAL CHARACTERISTICS
SYMBOL VDD IVDD PARAMETER Operating Range VDD Supply Current
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = VOUT = 5V, VDD = 16.1V, VUV = 0.4V, VOV = 0.2V, GATE Open, unless otherwise specified.
CONDITIONS
q
MIN
q q
TYP 3.0 3.6 0.75
MAX 30 4.0 5.6 1 230 0.25 1
UNITS V mA mA V mV V A
VIN = 1.2V, VOUT = 1.1V, VDD = 12.3V, GATE Open VIN = 18V, VOUT = 17.9V, VDD = 29.1V, GATE Open VOUT = 4.9V, ISTATUS = 1mA VOUT Falling, Measured with Respect to VIN IST = 5mA, VOUT = 4.9V, Status On VST = 30V, Status Off, VIN = 4.9V
Status Functions VGIS VIOGF VSTON ISTOFF Min Gate Voltage for Turning On Status VIN to VOUT Fault Voltage with Open Gate Status Pin On Voltage Status Pin Leakage Current
q
185
q q
210 0.13 0.04
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD * 120C/W)
TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25C unless otherwise specified. Undervoltage Threshold vs Temperature
310 308 306 304 VIN = 1.2V VIN = 5V VIN = 12V VIN = 20V 305 303 301
VUV(TH) (mV)
VOV(TH) (mV)
302 300 298 296 294 292 290 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
VUV(TH) (mV)
50 25 0 75 TEMPERATURE (C) 100 125
UW
4351 G01
Overvoltage Threshold vs Temperature
VIN = 1.2V VIN = 5V VIN = 12V VIN = 20V 310 308 306 304 302 300 298 296 294 292 293 -50 -25 290
Undervoltage Threshold vs VIN
299 297 295
0
2
4
6
8
10 12 14 16 18 20 VIN (V)
4351 G03
4351 G02
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LT4351 TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25C unless otherwise specified. Overvoltage Hysteresis vs Temperature
25 VIN = 5V 20 18 16
Overvoltage Threshold vs VIN
310 308 306
OV HYSTERESIS (mV)
TURN-OFF DELAY (s)
304
VUV(TH) (mV)
302 300 298 296 294 292 290 0 2 4 6 8 10 12 14 16 18 20 VIN (V)
4351 G04
IVIN vs Temperature
2.0 1.9 1.8 1.7
IVDD (mA)
VIN = 1.2V VIN = 5V VIN = 12V VIN = 20V
1.5 1.4 1.3 1.2 1.1 1.0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
VGOFF (V)
IVIN (mA)
1.6
GATE Pin Turn On and Off Waveform with 10nF Capacitor Load
TURN ON
VSW 2V/DIV
VIN = 5V 50ns/DIV VOUT = 4.9V to 5.1V SQUARE WAVE
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4351 G07
Overvoltage Turn-Off Delay vs Overvoltage Overdrive
VIN = 5V
20
14 12 10 8 6 4 2
15
10
5
0 -50 -25
0 50 25 0 75 TEMPERATURE (C) 100 125 0 35 20 15 10 25 30 5 OV VOLTAGE ABOVE THRESHOLD (mV)
3451 G06
4351 G05
IVDD vs Temperature
4.5 VIN = 1.2V VIN = 5V VIN = 12V VIN = 20V 0.50 0.45 0.40 0.35 3.5 0.30 0.25 0.20 0.15 2.5 0.10 0.05 2.0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
Gate Off Voltage vs Temperature
4.0
VIN = 5V VOUT = 5V
3.0
VIN = 5V VOUT = 5.1V
0 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
4351 G08
4351 G09
Typical SW Pin Waveform
VSW 5V/DIV
TURN OFF
3451 G10
VIN = 5V L = 4.7H
500ns/DIV
3451 G11
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LT4351 TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25C unless otherwise specified. SW Pin Waveform at Maximum Boost Regulator Output Typical SW Pin Waveform
VSW 5V/DIV
VIN = 5V 4.7H INDUCTOR
PI FU CTIO S
GATE (Pin 1): MOSFET Gate Drive Pin. This pin is tied to the gate(s) of the external N-channel MOSFET(s). The GATE pin drives high when UV is above the VUV(TH) threshold, OV is below the VOV(TH) threshold and VIN is greater than OUT by 15mV. When not driven high, GATE actively pulls to GND. GATE can sink or source up to 600mA. VDD (Pin 2): Gate Drive Supply Pin. This is the supply pin for the gate drive amplifier. It is either generated by the onboard boost regulator or supplied externally. When turning on the MOSFET(s), a large high current pulse flows through this pin. Bypass the pin with a 1F capacitor placed in close proximity to the part. The voltage on this pin is also the feedback for the boost regulator. If the VDD voltage exceeds the VIN voltage by 10.7V, the boost switch is held off. VIN (Pin 3): Input Supply Pin. This pin is the supply pin for the control circuitry and the boost regulator. It is also one input in conjunction with OUT for controlling the MOSFET(s). Bypassing should include a low ESR/ESL capacitor placed in close proximity to the part. SW (Pin 4): Boost Regulator Switch Pin. This pin is the boost regulator switch output. It is connected to the boost inductor and the boost diode. Peak switch current is limited internally to 450mA. If an external VDD supply is used, leave this pin open. GND (Pin 5): Device Ground Pin. This pin is ground for the boost switch, gate driver as well as the control circuitry. Tie the VIN and VDD bypass capacitors and ground plane close to this pin to minimize the effects of switching currents on part performance.
UW
VSW 5V/DIV
10s/DIV
3451 G12
VIN = 5V 4.7H INDUCTOR
10s/DIV
3451 G13
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LT4351
PI FU CTIO S
OV (Pin 6): Overvoltage Shutdown Pin. This pin is used for input overvoltage detection. It is connected to a resistive divider from VIN. When the voltage exceeds the OV threshold (0.3V), GATE is pulled to GND disabling power transfer. In addition, the FAULT pin pulls low indicating a fault. Overvoltage detection has filtering on it to prevent false triggering. The filtering depends on the level of overdrive. Filtered tripping will occur when OV exceeds 0.3V. If OV exceeds 0.33V, the gate immediately turns off (no filtering). If overvoltage detection is not required, ground the OV pin. See Applications Information for further information. UV (Pin 7): Undervoltage Shutdown Pin. This pin is used for the undervoltage detect function. It is connected to a resistive divider from VIN. When the voltage is below the UV threshold, GATE pulls to GND disabling power transfer. In addition, the FAULT pin pulls low indicating a fault. When the UV pin voltage drops below the threshold, a 10A current is pulled from the divider to provide hysteresis. If undervoltage detection is not required, tie the UV pin to a voltage greater than 320mV and not greater than VIN. Do not force more than 9V on UV due to an internal clamp. See Applications Information for further information. FAULT (Pin 8): Fault Comparator Status Pin. This pin pulls low when a fault occurs. A fault has occured if the UV pin is below threshold or the OV pin is above threshold. The FAULT pin low indicates that there is a problem with the VIN (source) supply. GATE is pulled to GND during a fault, disabling the MOSFET(s) and prohibits common supply contamination. If the GATE pin goes to compliance (GATE equals the lesser of VDD - 2.3V or OUT + 7.4V) and VIN is greater than OUT by more than 0.21V, FAULT turns on as an indicator that the MOSFETs are probably not functioning. Leave this pin open if not used. STATUS (Pin 9): MOSFET Status Pin. This pin pulls low when GATE is above VIN by more than 0.7V and VIN is greater than OUT by 15mV. This indicates the MOSFET is on. Leave this pin open if not used. OUT (Pin 10): Common Supply Pin. This pin is connected to the supply common and is used in conjunction with VIN as one input controlling the MOSFET(s).
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LT4351
BLOCK DIAGRA
VIN
FROM INDIVIDUAL SUPPLY VOUT
4 SW
ENABLE
QSW
600ns ONE SHOT
+ -
7 RB R1 0.3V 6 RA OV COV 0.33V UV
R2
+ -
CUV
COVF
0.3V
+
5 GND
4351 BD
+
-
-
+
-
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TO COMMON SUPPLY 2 VDD 10.7V REG 3 VIN 1 GATE
+
ENABLE DRIVER
-
15mV
+ -
OUT 10
VIN
OPEN OUT MOSFET DETECT
+
ST
STATUS
9
-
FAULT 8
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LT4351
OPERATIO
Increasingly, system designers have to deal with multiple supply sources. The multiplicity may provide parallel, redundant supplies for increased reliability or provide a means of connecting disparate supplies. In all cases the desire is for behavior like a diode but with no loss or voltage drop. ORing diodes have been the conventional means of connecting these supplies. The disadvantage of this approach is that diodes introduce efficiency loss because of their forward voltage drop. This variable voltage drop also degenerates supply tolerance. Additionally, diodes provide no information concerning the status of the sourcing supply. Separate control must also be added to ensure that a supply that is out of range is not allowed to affect the common supply. The LT4351 eliminates these problems by using N-channel MOSFETs as the pass elements. The MOSFET is turned on when power is being passed, allowing for a low voltage drop from the supply to the load. When the input source voltage drops below the output common supply voltage it turns off the MOSFET, thereby matching the function and performance of an ideal diode. The LT4351 drives either a single MOSFET or dual backto-back MOSFETs. Dual MOSFETs are chosen to eliminate current flow from the input supply to the output supply when the VIN voltage is greater than OUT. A driver amplifier monitors the input (VIN) and output (OUT) and controls the MOSFETs. If VIN exceeds OUT by 15mV, GATE goes high and turns on the MOSFET(s) allowing for power passage. Undervoltage and overvoltage comparators CUV, COV and COVF also control power passage. A resistive divider in conjunction with the UV and OV pins sets appropriate thresholds such that the MOSFET(s) is off when the UV pin is below 300mV or OV pin is above 300mV. To help deal with the transients on the supply lines, the UV input has current hysteresis. When the UV voltage drops below the 300mV threshold, a 10A current is pulled from the pin. Thus the user can set the hysteresis level through appropriate values in the divider. Overvoltage shutdown occurs in two stages. The first occurs when the OV pin exceeds the 300mV reference.
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When OV just exceeds the reference, an internal capacitor starts charging, delaying the signal to turn off the MOSFET(s). The second occurs when the OV pin exceeds 330mV. The OVF comparator will immediately trip pulling GATE to GND. This affords a delay inversely proportional to the amount of overdrive. This also provides for glitch immunity without compromising response time in the event of a serious overvoltage condition. The FAULT output indicates the status of the COV, COVF and CUV comparators. It pulls low during a fault condition. It also pulls low when GATE is at compliance and VIN > OUT by more than 0.21V indicating a probable nonfunctioning MOSFET. Compliance occurs when GATE is at the lesser of OUT + 7.4V or VDD - 2.3V. FAULT derives its drive from the greater of VIN or OUT. It is active if VIN or OUT is greater than 0.9V. If VIN or OUT is below this level, the output state is not guaranteed. The gate drive consists of a high current, wide bandwidth amplifier (Driver). When the amplifier is enabled, it attempts to regulate the GATE voltage such that the voltage across the MOSFET(s) is approximately 15mV. If the MOSFET(s) on resistance is so high as to prevent regulation, then GATE goes to compliance and the MOSFET(s) fully turns on. The inputs to the amplifier are VIN and OUT. The GATE pin sources current from VDD and sinks current to GND. The maximum GATE to VIN voltage is the lesser of VDD - 2.3V or 7.4V above VOUT or VIN (internal clamp voltage). The STATUS comparator, ST, pulls low when GATE exceeds VIN by 0.7V. This occurs when VIN > OUT + 15mV. The STATUS pin pulls low as an indication that power is passing through the MOSFET(s). If VIN is greater than OUT by 0.21V and GATE > VIN + 7.4V or at compliance (GATE = VDD - 2.3V), STATUS will go high as an indication of a likely open MOSFET. FAULT will pull low in this state indicating the probable fault. The gate drive amplifier and STATUS function derive power from VDD. The circuit requires VDD > 2.5V. If VDD is present, the gate drive amplifier and STATUS are active independent of the state of VIN. If in a fault, GATE pulls
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LT4351
OPERATIO
actively low. In the event of VDD collapse there still is an active pull-down (though of lesser strength) of GATE powered from OUT, guaranteeing turn off. The on-chip boost regulator uses a constant off-time control scheme. When VDD is below the regulation trip voltage, the switch turns on after a 600ns off-time. When the switch turns on current ramps up in the inductor until the current limit is reached (450mA). The switch turns off
APPLICATIO S I FOR ATIO
Setting Fault Thresholds
The gate drive amplifier implements the ideal diode function. The fault comparators (UV and OV) prevent out of range input voltages from affecting the output by disabling the amplifier during these conditions. Think of the UV and OV as gating the ideal diode function, something a regular diode can't do. A resistive divider from VIN to UV and one from VIN to OV are the usual way of setting the FAULT thresholds. For UV the resistor values are set by:
UVHYST IUVHYST VUV R1 = * R2 UVFAULT - VUV R2 =
where UVHYST is the desired undervoltage hysteresis at the input. UVFAULT is the desired undervoltage trip voltage
VIN R2 UV VUV 300mV VIN R2 UV VUV 300mV
R1
IHYS 10A
R1
IHYS 10A
4351 F01
UV TURNING ON
UV TURNING OFF
Figure 1
Figure 2
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and the inductor's current flows through the external diode to charge up the VDD capacitor. If VDD is still too low, the switch turns on again after a fixed off-time of 600ns. The boost regulator regulates VDD to approximately 10.7V above VIN. When VDD is above this level, the SW transistor turn-on is disabled. When VDD falls below this level by the hysteresis level, the SW transistor is allowed to turn on. There is approximately 0.15V of hysteresis. at the input. VUV is the part undervoltage trip point (0.3V) and IHYSTUV is the undervoltage hysteresis current (10A). See Figure 1. The divider on the OV pin is a straightforward resistive divider (Figure 2): OV RB = FAULT - 1 RA VOV 0.3V RA = RA ,RB Divider Current where OVFAULT is the desired overvoltage trip point at the input and VOV is the OV pin threshold (0.3V). The OV pin has 7mV of voltage hysteresis at room. It is possible to do both dividers together using only three resistors though with more interdependence in components (Figure 3). The input bias current for UV and OV is less than 200nA, so keep resistor values less than 10k.
VIN
VIN
R3 UV
VIN RB OV VOV 300mV
R2B
R2 OV R1
4351 F03
R2A C1 R1
4351 F04
UV
RA
4351 F02
Figure 3
Figure 4
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LT4351
APPLICATIO S I FOR ATIO
In that case the resistor values are set by:
UVHYST IUVHYST UV VUV - FAULT * VOV OVFAULT * R3 R2 = UVFAULT - VUV VOV * UVFAULT * R3 R1 = OVFAULT * (UVFAULT - VUV ) R3 =
Hysteresis helps prevent erratic behavior due to the noise on VIN. Two of the most common noise sources are: VIN dipping when the MOSFETs first turn on and draw down the voltage on the VIN capacitors, and the boost regulator switch turning on and drawing current from the VIN capacitors. Use low ESR capacitors for VIN and OUT filtering. Note that because the UV pin uses current hysteresis, placing a capacitor on UV to ground to filter noise will reduce the effective hysteresis. Filtering can be achieved by splitting the R2 resistor as shown in Figure 4. To defeat undervoltage fault detection, the UV pin should be tied higher than 0.33V. UV can be tied to VIN provided VIN < 9V. Overvoltage fault detection can be defeated by grounding the OV pin. Do not exceed VIN.
INPUT REFERRED OVERVOLTAGE FAULT: GATE LOW OVFAULT OVERVOLTAGE FILTERED FAULT GATE CONTROLLED BY VIN - VOUT UVFAULT + UVHYST UVFAULT UNDERVOLTAGE HYSTERESIS UNDERVOLTAGE FAULT: GATE LOW VOV > 0.3V VOV = 0.3V
4351 F05
OV REFERRED
Figure 5. Graphical Representation of the UV and OV Functions
External Shutdown To externally turn off the MOSFETs, such as to disable the supply, use an open-collector transistor pulling down on the UV pin. Note this will not turn off the boost regulator which will continue to operate.
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Boost Regulator The boost regulator will start working as soon as VIN is greater than 0.85V. The regulator will supply all the current for the gate drive amplifier. While the amplifier itself requires only about 3mA, larger current pulses are required when charging the MOSFET gate. The reservoir capacitor on VDD will provide this current (Figure 6).
VIN LT4351 SW QSW D2 GND
4351 F06
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L1 D1 VDD CDD
Figure 6
UV REFERRED
VUV = 0.33V VUV = 0.3V VUV < 0.3V
The regulator performance is relatively insensitive to the inductor value. The inductor value does control the frequency of operation. A 4.7H inductor is recommended for VIN voltages less than 10V and 10H for VIN voltages greater than 10V. Several inductors that work well with the LT4351 are listed in Table 1. Many different sizes and shapes are available. Consult each manufacturer for more detailed information and for their entire selection of related parts. The switching frequency for the boost regulator is around 1MHz so ferrite core inductors should be used to obtain the best efficiency. The inductor must handle a peak current of 0.7A minimum and have a DC resistance of 0.5 or less. Shielded inductors are recommended to reduce the noise due to inductive switching.
Table 1. Recommended Inductors
PART NUMBER DS1608C-472 DS1608C-103 CDRH4D18-4R7 CDRH4D28-100 LMNP045B4R7N LMNP045B100M IND (H) 4.7 10 4.7 10 4.7 10 MAX DCR (m) 90 160 125 95 50 52 VENDOR Coilcraft (847) 639-6400 www.coilcraft.com Sumida (847) 956-0666 www.sumida.com Taiyo Yuden (408) 573-4150 www.t-yuden.com
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LT4351
APPLICATIO S I FOR ATIO
For VIN less than 2V, choose a DC resistance less than 0.2. Note that VDD current referred to the input supply is higher. A first order approximation of the input current is:
10.6 IVDD IVINVDD = 1 + * VIN 80%
Under normal operation, the VDD current is under 10mA and the boost regulator operates in Burst Mode operation. If any additional load is added, you must ensure that the regulator is capable of supplying that load. As the load is increased, the boost regulator will switch into continuous mode operation. Further increases in load will collapse the boost regulator voltage. Operating the regulator with increased load will cause increased IC power dissipation and temperature, which must be taken into consideration. A 100ns delay from detecting the switch current limit to turning off the power switch produces an overshoot of the inductor current from the 0.45A switch limit. The amount of overshoot depends on the boost regulator inductance. Choosing an inductor that can handle 0.75A peak current will be sufficient for the recommended inductors. Diode Selection Schottky diodes, with their low forward voltage drop and fast switching speed, are the best match for the LT4351 boost regulator. Select a diode that can handle 0.75A peak current and a reverse breakdown of 15V greater than the maximum VIN.
VIN 200mV
10s/DIV
4351 F07a
Figure 7a. Example of Input Voltage Ringing with Low CIN Capacitor at MOSFET Turn Off
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VDD Capacitor Selection Low ESR (Equivalent Series Resistance) capacitors should be used on VDD to minimize the output ripple voltage. Multilayer ceramic capacitors are the best choice, as they have a very low ESR and are available in very small packages. Always use a capacitor with a voltage rating at least 12V greater than VIN. Capacitors Two types of input capacitors are generally needed for the LT4351. The first is a large bulk capacitor that takes care of ringing associated with inductance of the input supply lines and provides charge for the load when switching the MOSFET. The input parasitic inductance in conjunction with CB and its ESR create an LCR network. The input LCR can be stimulated by the boost regulator switch current or load current transients when the MOSFETs are on. To reduce ringing associated with input inductance, CB should be:
CB 4 * LIN RESR2
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where CB is the capacitor value, RESR is the capacitor's ESR and LIN is the inductance of the input lines. While damped ringing is not necessarily bad, it may produce unexpected results as the LT4351 ideal diode reacts to the varying VIN to OUT voltage. Typically an electrolytic or tantalum low ESR capacitor would be used. Figure 7a illustrates VIN for a low value of CB and Figure 7b shows it with a correctly sized value.
VIN 200mV
10s/DIV
4351 F07b
Figure 7b. Example of Input Voltage with Sufficient CIN Capacitor at MOSFET Turn Off
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LT4351
APPLICATIO S I FOR ATIO
As an example, for 500nH of inductance and RESR of about 100m, then:
4 * 500nF = 200F 0.12 Check vendor data for ESR and iterate to get the best value. Additional CB capacitance may be required for load concerns. C
If the boost regulator is being used, place a 10F low ESR ceramic capacitor from VIN to GND. Place a 10F and a 0.1F ceramic capacitor close to VIN and GND. These capacitors should have low ESR (less than 10m for the 10F and 40m for the 0.1F). These capacitors help to eliminate problems associated with noise produced by the boost regulator. They are decoupled from the VIN supply by a small 1 resistor as shown in Figure 8. The LT4351 will perform better with a small ceramic capacitor (10F) on OUT to GND.
VIN LIN PARASITIC
CV3 10F CB
1 CV1 10F CV2 0.1F
GATE VIN LT4351
GND
4351 F08
Figure 8. VIN Capacitors
External Boost Supply The VDD pin may be powered by an external supply. In this case, simply omit the boost regulator inductor and diode and leave the SW pin open. Suitable VDD capacitance (minimum of a 1F ceramic) should remain due to the current pulses required for the gate driver. The VDD current consists of 3.5mA of DC current with the current required to charge the MOSFET's gate which is dependent on the gate charge required and frequency of switching. Typically the average current will be under 10mA. MOSFET Selection The LT4351 uses either a single N-channel MOSFET or back-to-back N-channel MOSFETs as the pass element.
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Back-to-back MOSFETs prevent the MOSFET body diode from passing current. Use a single MOSFET if current flow is allowable from input to output when the input supply is above the output (limited overvoltage protection). In this case the MOSFET should have a source on the input side so the body diode conducts current to the load. Back-to-back MOSFETs are normally connected with their sources tied together to provide added protection against exceeding maximum gate to source voltage. Selection of MOSFETs should be based on RDS(ON), BVDSS and BVGSS. BVDSS should be high enough to prevent breakdown when VIN or OUT are at their maximum value. RDS(ON) should be selected to keep within the MOSFET power rating at the maximum load current (I2 * RDS(ON)) BVGSS should be at least 8V. The LT4351 will clamp the GATE to 7.5V above the lesser of VIN or OUT. For back-toback MOSFETs where sources are tied together, this allows the use of MOSFETs with a VGS max rating of 8V or more. If a single MOSFET is used, care must be taken to ensure the VGS max rating is not exceeded. When the MOSFET is turned off, the GATE voltage is near ground, the source at VIN. Thus, MOSFET VGS max must be greater than VIN(MAX). If a single MOSFET is used with source to VIN, then BVGSS should be greater than the maximum VIN since the MOSFET gate is at 0.2V when off. The gate drive amplifier will attempt to regulate the voltage across the MOSFETs to 15mV. Regulation will be achieved if:
RDS < RDS < 15mV for two MOSFETs and 2 * ILOAD 15mV for a single MOSFET ILOAD
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This requires very low RDS values. This may be achieved by paralleling MOSFETs, but be careful to keep interconnection trace resistance low. In the event that regulation cannot be achieved, the gate drive amplifier will drive GATE to its clamp and achieve the best RDS possible at that level.
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LT4351
APPLICATIO S I FOR ATIO
STATUS The STATUS pin sinks current when the input (VIN) is above output (OUT) by 15mV and GATE is above VIN by 0.7V. This will normally indicate that power is being passed though the MOSFETs. In the event of a nonfunctional MOSFET, the GATE voltage will be driven high (to the GATE clamp voltage). If VIN is greater than OUT by more than 0.21V, the FAULT pin will sink current to signal the potential problem. There is no direct measurement or confirmation of current flowing in the MOSFETs. Current is shared between sources based on their voltage and series resistance. If precision load sharing is desired, the LTC4350 may be a more suitable part. Redundant Supplies The LT4351 is an improved solution for ORing redundant supplies because of its lower forward drop versus conventional diodes. The lower forward drop significantly improves overall efficiency, improves the voltage tolerance at the load and provides for a more accurate transition from supply to supply and more accurate load sharing between supplies.
BACKPLANE LT4351 BOARD LOAD LT4351
SYSTEM SUPPLY LOAD BATTERY
SOURCE 1
SOURCE 2
BACKPLANE
LT4351
BOARD
SOURCE 1
WALL ADAPTER
LT4351 LOAD SOURCE 2
4351 F09
Figure 9. Redundant Backplane Supplies
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ORing can be done either at the load or at the source. Figure 9 shows some examples. ORing at the load is usually the safest method since it protects against shorts in interconnects. The LT4351 tighter forward voltage tolerance makes it easier to balance current between similar supplies using the droop method. The droop method uses the supply voltage and series resistance in the power path to provide load sharing. In this case, size the MOSFET's RDS(ON) low to allow for regulation. ORing Disparate Supplies The LT4351 provides an easy solution for connecting together different types of power sources. Again because of the low forward drop, the efficiency of the system is improved and the voltage transition between supplies is more accurate. In addition, the undervoltage and overvoltage features of the LT4351 provide options for enabling and disabling the supplies that are not available from a common diode. Figure 10 shows some examples of connecting disparate supplies.
Isolated System Supply from Wall Adapter
WALL ADAPTER LT4351
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Isolated Battery Backup
WALL ADAPTER LT4351
+
LOAD
Three Source ORing Provides Protection Against Out of Range Supplies
LT4351
LT4351
LT4351
+
BATTERY LOAD SYSTEM SUPPLY
4351 F10
Figure 10
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13
LT4351
APPLICATIO S I FOR ATIO
Start-Up Considerations There is no inherent shutdown in the part. As VIN ramps up, the boost regulator starts at about 0.85V and becomes fully operational by 1.1V. The undervoltage and overvoltage comparators become accurate by 1.2V. The gate drive amplifier keeps GATE low during this period with either a passive pull-down, a weak active pull-down if OUT is greater than 0.8V or with the full gate drive sink if VDD is above 2.2V. Once VIN is greater than 1.2V and VDD is up, the part then operates normally. The UV and OV pins will control the enabling of the gate driver and once enabled, the VIN to OUT voltage controls MOSFET turn on. If VDD is still being charged when the gate driver turns on the MOSFET, the GATE pin tracks with the VDD increase until it reaches either the gate clamp voltage or the compliance of the gate driver. If VDD is present without VIN or OUT, the GATE pin actively sinks low. Power Dissipation The internal power dissipation of the LT4351 is comprised of the following four major components: DC power dissipation from VIN, DC power dissipation from VDD, the dissipation in the boost switch including the base drive, and dynamic power dissipation due to current used to charge and discharge the MOSFETs. The DC components are: PDCVIN = IVIN * VIN PDCVDD = IVDD * VDD
0.30
0.25
PBOOST (W)
L = 10H 0.20 L = 4.7H 0.15
PBOOST (W)
0.10
0
5
10 VIN (V)
15
20
4351 F11
Figure 11. PBOOST(MAX)
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Figure 11 shows the internal dissipation of the boost regulator as a function of VIN and inductor value. Figure 11 represents the worst-case condition with the regulator on all the time, which does not occur in normal practice. Since the boost regulator supplies current for VDD, the current is the VDD supply current (3.5mA) plus the average current to charge the gate. For a gate charge of 50nC at a 10kHz rate, this adds 0.5mA of current. The power dissipated by the boost regulator to supply the 4mA is shown in Figure 12, representing a more typical situation. Finally, the gate driver dissipates power internally when charging and discharging the gate of the MOSFETs. This power depends on the input capacitance of the MOSFETs and the frequency of charge and discharge. The power associated with this can be approximated by: V PGATE = fG * VDD * QG * 1 - IN 16 where QG is the required gate charge to charge the MOSFET to the clamp voltage (7.4V) and fG is the frequency at which the gate is charged and discharged. Normally fG is low and the resulting power would be very low. Figure 13 shows PGATE for a 50nC gate charge at a 1kHz rate. Total power dissipation is the sum of all of PDCVIN, PDCVDD, PBOOST and PGATE. Figure 14 is representative of the total power dissipation of a typical application at steady state.
0.025 L = 4.7H 0.020 0.015 0.010 0.005 0 5 10 VIN (V)
4351 F12
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Figure 12. PBOOST(TYP)
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LT4351
APPLICATIO S I FOR ATIO
0.004 fGATE = 1kHz QG = 50nC 0.003
POWER (W)
PGATE (W)
0.002
0.001 0.08
0
0
5
10 VIN (V)
15
20
4351 F13
Figure 13. PGATE vs VIN (VDD = VIN + 10.7)
The die junction temperature is then computed as: TJ = TA + JA * PTOTAL where TJ is the die junction temperature, TA is the ambient temperature, JA is the thermal resistance of the part (120C/W) and PTOTAL is ascertained from the above. Therefore, a 0.1W power dissipation causes a 12 degree temperature rise above ambient. Design Example The following demonstrates the calculations involved for setting design components for a 5V system that requires 5A. Two supplies are used to do this. The VIN supply will be deemed in spec when it is within 5% of nominal. Allow 5% of hysteresis for UV. So, UVFAULT = 4.75V, UVHYST = 0.25V OVFAULT = 5.5 Two separate resistive dividers are used. For the UV divider: UVHYST 0.25V = = 25k (Use 24.9k ) IUVHYST 10A R2 * VUV 24.9k * 0.3V R1 = = UVFAULT - VUV 4.75V - 0.3V R2 = R1 = 1.68k. The closest 1% value is 1.69k
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0.16 VDD = VIN + 10 0.5mA GATE CURRENT 0.14 0.12 0.10 L = 10H L = 4.7H 0.06 0 5 10 VIN (V)
4351 F14
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Figure 14. Total Power (Typical)
The OV resistors are set as a straight resistive divider. If the current in the RA, RB divider is 200A, then:
RA = then OV 5.5 RB = FAULT - 1 RA = - 1 1.47k 0.3 VOV RB = 25.48k use 25.5k 0.3V = 1.5k use 1.47k (1%) 200A
For regulation, the MOSFETs must have: RDS < 15mV = 1.5m 2 * 5A
This very low value cannot be accomplished with a single set of MOSFETs so a decision must be made whether to use multiple MOSFETs or to live with an unregulated offset. Since low m RDS(ON) is available, the IR drop using a single FET would still be acceptable. For RDS(ON) = 4m the drop is 2 * 5A * 4m = 40mV. The finished schematic is shown in Figure 15.
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LT4351
APPLICATIO S I FOR ATIO
VIN 5V
R2 24.9k 1% 4.7H RB 25.5k 1% R1 1.69k 1%
10F
RA 220F 1.47k 1%
Figure 15. 5V/5A Design Example
Layout Considerations There are two considerations for board layout. The first is that VIN and VDD bypass capacitors should be as close to the part as possible. The GND pin should represent the common tie point. The resistive dividers for UV and OV should tie here as well.
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Si4838DY OUT 1 10F 0.1F 7 UV LT4351 OV SW VDD GND 5
4351 F15
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10F 3 VIN 1 GATE 10 OUT 5V
6 4 MBR0530 MBR0530 1F 2
2k STATUS FAULT 9 8
2k
Take care that current flow to the load (both through VIN and GND), does not inadvertently produce errors due to IR drops in PCB traces. Keep the traces to the MOSFETs wide and short and close to the part. The PCB traces associated with the power path through the MOSFETs should have low resistance.
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LT4351
TYPICAL APPLICATIO S
Lead Acid Battery Backup
CHARGER
12V LEAD-ACID BATTERY
+
R2 12.7k 1% 10H RB 73.2k 1% R1 365 1% 10F 0.1F 7 UV
10F
MBR0530 RA 1.5k 1%
+
220F
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Si4408DY OUT 1 3 VIN 1 GATE 10 OUT 10F
14V POWER SUPPLY
LOAD
6 4 MBR0530 1F 2
LT4351 OV SW VDD GND 5
4351TA02
10k STATUS FAULT 9 8
10k
UVFAULT = 10.8V OVFAULT = 15V
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LT4351
TYPICAL APPLICATIO S
5V Redundant Supply with External VDD
5V SOURCE 1 R2 24.9k 1% R1 1.69k 1% 10F 0.1F 7 3 VIN UV LT4351 OV SW VDD GND 5
4351 F15
+
100F
12V SOURCE
2ND 5V SOURCE 2ND LT4351 CIRCUIT 2ND 12V SOURCE
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Si4838DY
10F 1 GATE 10 OUT
10F RB 25.5k 1% RA 1.47k 1%
6 4 2 1F
2k STATUS FAULT 9 8
2k
1ST SOURCE
COMMON
LOAD
4351 TA03
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LT4351
PACKAGE DESCRIPTIO U
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127 (.035 .005) 3.20 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 0.497 0.076 (.0196 .003) REF DETAIL "A" 0 - 6 TYP 12345 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.17 - 0.27 (.007 - .011) TYP 0.127 0.076 (.005 .003)
MSOP (MS) 0603
5.23 (.206) MIN
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
1.10 (.043) MAX
0.86 (.034) REF
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.50 (.0197) BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT4351
TYPICAL APPLICATIO U
Primary Battery with Secondary Battery Backup
Si4408DY OUT 1 R2 40.1k 1% 10H R1 1.07k 1% 10F 0.1F 7 3 VIN UV LT4351 OV SW VDD GND 5 UVFAULT = 11.8V STATUS FAULT 9 8 100k 5% 10k 5% 10k 5% 1 GATE 10 OUT 10F 6 4 MBR0530 1F 2 Si4408DY OUT 120k 5% 10F 0.1F 7 10H 1N914 300k 5% 1 3 VIN UV LT4351 OV SW VDD GND 5 POWER IS SWITCHED TO BATTERY2 WHEN BATTERY1 DROPS TO 11.8V
4351TA04
CHARGER
+
12.6V BATTERY1
+
100F
MBR0530 10F
CHARGER
+
12.6V BATTERY2
10F 1 GATE 10 OUT
100F
LOAD
6 4
10k STATUS FAULT 9 8
10k
+
100F
MBR0530 10F
MBR0530 1F
2
RELATED PARTS
PART NUMBER LTC1473 LTC4350 LTC4412 DESCRIPTION Dual PowerPath Switch Driver Hot Swappable Load Sharing Controller Low Loss PowerPath Controller in ThinSOTTM
TM
COMMENTS Switches and Isolates Sources Up to 30V Output Voltage 1.2V to 12V, Equal Load Sharing P-Channel MOSFET, 3V to 28V Range
PowerPath and ThinSOT are trademarks of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 1203 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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